Description
We are seeking a qualified Signal and Power Integrity Engineer to help us develop our next generation ASIC packaging. You will define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.
Responsibilities:
- Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
- Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
- Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
- Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
Minimum Qualifications:
- Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 2+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 0+ years of related experience.
- Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis.
- Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
- Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows.
- Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.
Preferred Qualifications:
- Experience with articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
- Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
- Experience with die-to-die interfaces (UCIe or proprietary).
- Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
- Experience with Vector Network Analysis.
- Experience with IBIS.
Benefits:
- Medical, dental and vision insurance
- 401(k) plan with a Cisco matching contribution
- Paid parental leave
- Short and long-term disability coverage
- Basic life insurance
- Paid time away (10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees)
- Flexible vacation time off program
- 80 hours of sick time off provided on hire date and each January 1st thereafter