Senior Mask Design Engineer – Hardware

We are seeking a Senior Mask Design Engineer to collaborate with Package Technical Lead and different design teams in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA products.

Responsibilities:

• Collaborate cross-functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solutions for product packages in tight schedules.
• Perform physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies to evaluate package design goals for size, cost, and system performance.
• Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists.
• Propose layout design trade-offs to the PTL for resolution and implementation.

Requirements:

• B.S. Electrical Engineering or equivalent experience.
• Minimum of 5+ years proven experience in Mask and Layout Design.
• Deep understanding of layout concepts in submicron CMOS technologies.
• Expertise with Cadence layout tools, particularly Virtuoso.
• Knowledge of Integrity auto-routing is a plus.
• Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.
• Proficient in scripting languages like Perl, Python, Skill, etc.
• Knowledge of DRC and LVS checking flows, ability to customize decks.
• Knowledge of APD package layout tool is a plus.
• Good understanding of packaging technology is useful.
• Excellent teamwork and interpersonal skills.