Senior Mask Design Engineer - Hardware

We are seeking a Senior Mask Layout Design Engineer to join our growing team of diverse individuals working on the latest generation chiplet interface projects.

The successful candidate will perform physical layout for mixed-signal functions, including top-level high-speed datapaths and high-speed clocking designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.

Key responsibilities:

• Perform physical layout for mixed-signal functions
• Work closely with mixed-signal design engineers to customize designs for integration in VLSI products
• Participate in floor planning, custom layout, and verification against design rules and schematics

Requirements:

• BSEE or equivalent experience
• Minimum of 5+ years of industry experience in Mask and Layout Design
• Experience with FinFET technology
• Expertise with Cadence custom circuit design tools, particularly Virtuoso
• Ability to work independently and effectively in a team
• Good interpersonal skills, enthusiasm, and positive energy
• Scripting languages like Perl, Python, Skill are a plus
• Knowledge of DRC and LVS checking flows, ability to customize decks