Senior Mask Layout Design Engineer

We are looking for a Senior Mask Layout Design Engineer to join our team responsible for handling challenging high-speed mixed-signal circuit designs.

You will perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.

You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.

Job duties will include floor planning, custom layout and verifying against design rules and schematics.

Requirements:

• BSEE or equivalent experience
• Minimum of 5+ years of relevant mask design / layout experience
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies; expertise with Cadence custom circuit design tools - particularly virtuoso.
• Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield
• Ability to communicate in spoken and written English, with good communication skills, enthusiasm and positive energy.
• Proficiency in scripting languages like perl, python, skill, etc.;
• Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks.