Description
We are looking for a Senior Mask Layout Design Engineer to join our growing team of diverse individuals. As a Senior Mask Layout Design Engineer, you will be responsible for performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools.
You will work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. You will also take part in floor planning, custom layout and verifying against design rules and schematics.
To be successful in this role, you will need to have a BSEE or equivalent experience and a minimum of 8+ years industry experience. You should have a deep understanding of analog circuit layout concepts in submicron CMOS technologies and be an authority with Cadence custom circuit design tools.
You will also need to have experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield. Good interpersonal skills, passion and positive energy are essential for this role.
You will also be eligible for equity and benefits.