Senior Mask Layout Design Engineer

NVIDIA is seeking a Senior Mask Layout Design Engineer to join a growing team of diverse individuals responsible for handling high-speed mixed-signal circuit designs.

The successful candidate will perform physical layout for mixed-signal functions like PLLs, high-speed SerDes, and Analog to Digital converters in sub-micron CMOS technologies using Cadence tools. They will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products, participate in floor planning, custom layout, and verify against design rules and schematics.

To be considered, candidates should have:

• A BSEE or equivalent experience
• At least 5 years of validated experience in Mask and Layout Design
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies
• Expertise with Cadence custom circuit design tools, particularly Virtuoso
• Experience with verification tools such as Dracula, Hercules, Calibre, and Primeyield
• Strong interpersonal skills and the ability to work successfully in a team
• Proficiency in scripting languages like Perl, Python, and Skill
• Knowledge of DRC and LVS checking flows and the ability to customize decks