Description

We are seeking a Validation / Verification Eng, Manager to lead a lab team validating memory IP that ships in products worldwide.

You will lead first silicon bring-up and validation for DDR6, DDR5, LPDDR6/X, LPDDR5/5X, MRDIMM, and HBM test chips.

Responsibilities:

Lead first silicon bring-up and validation for various memory interfaces
Perform electrical characterization including eye diagrams, jitter measurements, timing margins, and signal integrity analysis
Drive debug and root cause analysis of silicon, firmware, and board issues using lab instrumentation and cross-functional collaboration
Build automated validation frameworks using Python and C/C++ to improve test efficiency and data collection
Lead multilayer PCB design for characterization platforms and customer evaluation kits
Manage team hiring, staffing, resource allocation, morale and audit preparation while growing technical capability
Work alongside cross-functional teams to weigh business impacts and make critical decisions

The Impact You Will Have:

Ensure Synopsys memory interface IP products meet performance and reliability standards before customer deployment
Implement efficiency improvements and process changes to a team of 20+ staff across 3+ labs
Reduce time to market by building reusable test infrastructure that accelerates validation across IP generations
Provide silicon-proven characterization data that gives customers confidence to integrate Synopsys IP
Identify and resolve issues early, preventing costly re-spins and customer escalations
Grow a high-performing validation team in Nepean that becomes a center of excellence for memory IP
Influence design decisions by feeding back real-world silicon behavior to architecture teams

Requirements:

Bachelor's degree in Electrical Engineering or equivalent technical field
8+ years of hands-on silicon validation experience with memory interfaces such as DDR, LPDDR, or HBM
3+ years managing engineering teams, including hiring and resource allocation
Deep understanding of JEDEC specifications, jitter analysis, timing margins, and electrical characterization
Proficiency in Python and C for test automation and hardware validation scripting
Experience with ATE testers such as Teradyne, LTX/Credence, Advantest
Board design experience including multilayer PCB development, experience with automotive qualification standards or reliability testing is a plus
Experience in scheduling, event planning with vendors of all sorts

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.