Senior Physical Verification Engineer

NVIDIA is hiring a Senior Physical Verification Engineer to lead signoff-quality verification for advanced silicon programs.

You will drive physical verification strategy and closure for complex designs, working across implementation, methodology, and signoff teams to achieve tapeout readiness.

Responsibilities:

• Own physical verification closure for major blocks or full-chip designs through tapeout.
• Lead debugging of complex DRC, LVS, and reliability-related issues and drive high-quality resolution.
• Define verification check plans, signoff criteria, and closure priorities with cross-functional teams.
• Partner with physical design, custom design, and CAD teams to improve quality and turnaround.
• Drive automation, methodology improvements, and best practices for scalable PV execution.
• Review results, coach team members, and help reduce repeated classes of violations.

Requirements:

• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
• 5+ years of experience in physical verification, backend implementation, or ASIC signoff.
• Deep knowledge of DRC, LVS, physical signoff methodology, and tapeout flows.
• Strong experience with industry-standard physical verification tools and foundry rule decks.
• Proven ability to debug and close complex verification issues on large designs.
• Strong scripting and automation skills.
• Excellent communication and cross-team execution skills.

Preferred Qualifications:

• Experience owning full-chip PV signoff at advanced nodes.
• Familiarity with reliability, density, fill, ERC, or other manufacturing-related signoff checks.
• Experience leading methodology improvements across teams.