ASIC Physical Design Intern - 2027

As an ASIC Physical Design Intern at NVIDIA, you will work on tasks from RTL frozen to tape out, including synthesis, formal verification, constraints definition, timing closure/sign-off, and study on the timing impact of process and related methodology work.

Responsibilities:

• Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan
• Synthesis, RTL/netlist quality check, formal verification, function ECO creation
• Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure
• Work with PR engineers for chip implementation to achieve full chip timing closure
• Develop and improve entire timing closure flow from frontend to backend, flow automation development
• Methodology development in the above areas

Requirements:

• Currently pursuing a Master's or PhD degree in a relevant or related field
• Strong knowledge in IC design
• Passionate about technology research and IC backend
• Self-driven, good learning ability, good teamwork
• Excellent communication skills, proficient in English reading and writing

Preferred qualifications:

• Experience in IC backend implementation
• Hands-on experience with EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC)
• Proficient user of Python or TCL