Applications Engineer - ICV Runset Development

You will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build.

What You'll Be Doing

• Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond
• Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks
• Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases
• Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts
• Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track
• Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques
• Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market

The Impact You Will Have

• Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise
• Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space
• Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip
• Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects
• Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team
• Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes
• Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards

What You'll Need

• B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline
• 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development
• Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools
• Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes
• Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield
• Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus
• Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms