ASIC DFT Engineer

We are seeking a highly motivated ASIC DFT Engineer to join our Memory PHY development team and drive DFT implementation activities.

The successful candidate will be responsible for architecting, implementing, and validating test methodologies to ensure high manufacturing quality, fault coverage, and production yield.

Key responsibilities include:

• Defining and implementing DFT features such as Scan, Compression, MBIST, LBIST, Boundary Scan (JTAG), and ATPG flow development.
• Collaborating closely with Design, Verification, Physical Design, and Product Engineering teams throughout the ASIC development lifecycle.
• Performing DFT synthesis, scan insertion, pattern generation, fault coverage analysis, test timing closure, and silicon bring-up support.

Requirements:

• BS/MS degree in Electrical Engineering or Computer Engineering.
• 3+ years of experience in DFT.
• Hands-on experience with DFT flows and tools.
• Good understanding of HBM, DDR, UCIe protocols is a plus.
• Good communication in both Mandarin and English.

At Synopsys, we offer a range of benefits including:

• Comprehensive medical and healthcare plans.
• Time away programs, including ETO and FTO.
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
• ESPP, allowing purchase of Synopsys common stock at a 15% discount.
• Retirement plans that vary by region and country.
• Competitive salaries.