Senior Circuit Silicon Correlation DFT Engineer

NVIDIA is seeking a Senior Circuit Silicon Correlation DFT Engineer to participate in groundbreaking processor design and debug in deep submicron technologies. You will work in a multi-functional team passionate about silicon characterization and correlation to pre-silicon performance and power models.

Responsibilities:

• Participate in processor design and debug in deep submicron technologies.
• Work in a multi-functional team on silicon characterization and correlation to pre-silicon performance and power models.
• Generate ATPG patterns for silicon speed path debug.
• Perform RTL and gate-level verification for ATPG and non-ATPG patterns.
• Correlate diagnosis results to map to real design failures and root cause them to feed learnings to pre-silicon design sign-off parameters.
• Conduct RAM correlation by studying RAM circuit failure mechanisms and understanding their limits on silicon.
• Bring more circuit understanding into RAM testing methods across RAM types, chips, and processes to improve correlation in the long run.
• Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM.

Requirements:

• BSEE required, MS preferred in Electrical or Electronics Engineering with 8+ years of experience.
• Good understanding of Design-for-Test (DFT) and logic design.
• Solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.
• Experience in bringing up RTL/gate-level simulation, writing test cases, and debugging.
• Basics of circuits and RAM functionality/architecture.
• Experience with VLSI simulation tools like VCS.
• Experience with pattern generation using tools such as Tessent.
• Proficiency in scripting languages like Python, Perl, Tcl, Make, and automation methods/algorithms.
• Prior experience in STA and basic understanding of circuit concepts.