ASIC Verification Engineer - Clocks

The NVIDIA Clocks Team is seeking an exceptional Senior ASIC Verification engineer with extensive experience in Design Verification to deliver high-quality clocking and reset logic for various units in SOC automotive and datacenter ASICs.

Key Responsibilities:

• Own validation of Clocking structures in Tegra automotive and datacenter products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix, and productization.
• Develop scalable solutions to tackle sophisticated problems that work across platforms.
• Utilize industry-standard tools and state-of-the-art verification methodologies, including coding in System Verilog, UVM, C++, Perl, Python, and NVIDIA custom compilers and tools.
• Collaborate closely with the clocks/reset architecture and design team to validate clocks/reset design.
• Coordinate with internal and external teams across time zones.

Requirements:

• BS or MS in EE/ECE or equivalent experience.
• 2+ years of relevant industry work experience.
• Good understanding of Logic Design and Architecture.
• Expertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.
• Exposure to block-level and system-level verification.
• Strong coding skills in System Verilog, scripting languages (Perl/Python), and C++.
• Ability to collaborate and work with multiple groups.
• Prior experience in implementing Test plans for pre-silicon platforms.
• Understanding of DFT/IST is optional.