Solutions Engineer - Sr Staff, DFT/ Design for Test

You will work as a Solutions Engineer - Sr Staff, DFT/ Design for Test at Synopsys, Bengaluru, Karnataka, India.

You have spent years deep in semiconductor design, and you know that getting a chip to tape-out is only half the story. The other half is making sure it can actually be tested at scale, in volume, without blowing up the schedule or the yield. You understand DFT not as a checkbox but as a discipline that makes or breaks manufacturability, and you have the hands-on experience with scan insertion, ATPG, and tool flows to prove it.

You are comfortable sitting across from a customer's design team, listening to their constraints, their timeline pressures, their tool frustrations, and walking out with a plan that turns those constraints into a working solution. You do not just demo tools, you configure them, script around their edges, and make them fit the problem. TCL, Python, Perl are not languages you look up, they are tools you reach for without thinking.

You translate well. Between customer requirements and R&D roadmaps. Between technical depth and executive summaries. Between what the tool can do today and what the customer needs by next quarter. At Synopsys, you will work on DFT solutions that shape how the industry builds and tests silicon, and the customers you support will remember the difference you made.

Responsibilities

• Work directly with semiconductor customers to understand their DFT challenges, design constraints, and tool flow requirements, then translate those into technical solutions using Synopsys DFT tools including TestMAX Manager
• Configure, customize, and deploy DFT tool flows tailored to customer designs, including scan insertion, ATPG, and verification using TestMAX ATPG, Formality, and VCS
• Deliver hands-on technical demos and proof-of-concept implementations that show customers exactly how the toolset solves their specific design and test problems
• Script automation solutions in TCL, Python, or Perl to streamline customer workflows, improve tool adoption, and address gaps in existing flows
• Collaborate with Account teams to gather requirements, align on customer priorities, and provide regular technical updates throughout the engagement lifecycle
• Partner with R&D to surface customer feedback, reproduce tool issues, and influence product roadmap decisions based on real-world design challenges
• Stay current on DFT methodologies, semiconductor design trends, and emerging test strategies to ensure the solutions you deliver remain relevant and scalable

The Impact You Will Have

• Enable customers to achieve faster time-to-market by delivering DFT solutions that reduce design iterations and improve test coverage
• Increase adoption and satisfaction with Synopsys DFT tools by making them work seamlessly within customer design environments
• Strengthen customer relationships and retention by becoming the trusted technical advisor who understands their design challenges and delivers results
• Influence the direction of Synopsys DFT product development by bringing real customer requirements and pain points directly to R&D
• Improve silicon yield and manufacturability across the industry by helping customers implement robust, scalable DFT methodologies
• Reduce customer support escalations by proactively solving tool flow issues and building automation that prevents common failure modes
• Protect and grow Synopsys' leadership position in semiconductor design by ensuring customers see measurable value from the toolset

Requirements

• Master's degree (M.Tech or equivalent) in Electrical Engineering, Computer Engineering, or a related technical field
• 8 to 12 years of hands-on experience in semiconductor design, DFT engineering, or related domains with direct exposure to VLSI design principles and design flows
• Deep working knowledge of Design for Testability methodologies, including scan insertion, ATPG, and DFT verification techniques
• Proficiency in scripting languages such as TCL, Python, or Perl for automation, tool customization, and workflow optimization
• Direct experience with semiconductor design tools and flows, exposure to TestMAX Manager, Formality, VCS, or TestMAX ATPG is a strong plus
• Demonstrated ability to work directly with customers, gather technical requirements, and deliver solutions that meet both technical and business objectives
• Strong analytical and problem-solving skills with a track record of diagnosing complex tool or design issues and finding practical paths forward