Architect Digital Design -High Speed Memory Interface IP- HBM/DDR/LPDDR

Overview

You will define the architecture for memory IP that powers AI accelerators, data center processors, and mobile SoCs used by millions of people.

Job Description

You have spent years building memory interface IP that has to work at the bleeding edge of performance, power, and reliability. You know that the difference between a memory controller that ships and one that gets redesigned six months later is usually an architectural decision made early, and you are the kind of architect who sees around those corners.

Responsibilities

• Define and own the digital architecture for HBM, DDR, or LPDDR memory controllers, from high-level partitioning through RTL implementation strategy
• Drive design plans for complex memory interface blocks, balancing performance, area, power, and verification complexity across chip and block levels
• Collaborate with PHY teams, verification engineers, and product architects to ensure seamless integration and protocol compliance
• Evaluate and select design methodologies, tools, and flows that improve quality, reduce cycle time, and scale across product lines
• Mentor engineers on architecture decisions, RTL best practices, and debug strategies for high-speed memory interfaces
• Work directly with customers and internal stakeholders to align on feature requirements, timing constraints, and delivery milestones
• Review and guide RTL, testbenches, and verification plans to catch architectural issues before they become silicon problems

The Impact You Will Have

• Your architecture decisions will define the performance ceiling and power floor for memory IP used in next-generation AI and data center chips
• You will reduce time-to-market by building memory controllers that are easier to verify, integrate, and customize across multiple product variants
• The IP you help design will ship in millions of devices, from smartphones to high-performance computing systems
• You will elevate the technical depth of the team by mentoring engineers and establishing architectural patterns that scale
• Your ability to navigate ambiguity and make sound tradeoffs will directly influence which features ship and which get deferred
• You will help Synopsys maintain its leadership position in memory IP by driving innovations in HBM3, DDR5, LPDDR5X, and beyond
• The methodologies and design frameworks you put in place will improve quality and productivity across future memory IP projects

Requirements

• 12 - 15+ years of hands-on experience in ASIC digital design, with significant time spent on memory interfaces or high-speed IO protocols
• Deep technical knowledge of at least one of HBM, DDR, LPDDR, or similar memory protocols, including controller architecture, training, and PHY interface
• Proven ability to define and execute complex digital architectures from concept through RTL implementation and silicon bring-up
• Strong understanding of AMBA or similar on-chip interconnect protocols and how memory controllers integrate into SoC architectures
• Experience with advanced digital design tools and methodologies, including synthesis, timing closure, and low-power design techniques
• Excellent communication skills, you can explain a complex architectural tradeoff to a product manager, a verification lead, and a customer engineer without losing clarity
• Experience with HBM3, DDR5, or LPDDR5X is a strong plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries