Description
The Silicon One team at Cisco creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.
You will work with Cisco's best-in-class Silicon Photonics team, driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms.
We are looking for a hard-working and experienced Design Verification Lead to join our team and drive verification of Cisco's silicon photonics driver integrated circuits for the next generation of products for 100/200/400G per Lambda solutions.
Your Impact
- Define and lead verification methodology and standards across multiple projects, coordinating activities across multiple sites.
- Lead verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR/PAM4, Integrated drivers/TIA, and control functions.
- Review specifications, participate in design reviews, and influence architecture for testability and verification efficiency.
- Mentor and coach verification engineers, driving continuous improvement in technical skills and execution.
- Debug complex silicon and system-level issues during bring-up phases.
- Support post-silicon bring-up and optimize integration and performance.
Minimum Qualifications
- Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design Verification experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years in ASIC Design Verification experience.
- Experience in System Verilog, UVM, and verification methodologies.
- Experience owning and delivering verification for large-scale SoCs or subsystems.
- Experience leading verification teams or projects.
- Experience in scripting and automation such as Python, Perl, TCL, or Shell Scripts.
Preferred Qualifications
- Strong experience with UVM (Universal Verification Methodology) for developing scalable, reusable, and coverage-driven verification environments.
- Expertise in verification of SerDes IP, D2D PHY IP, ODSP & integrated transceiver features, CPU sub-system & Protocols (Ethernet, UCIE, UAL, SPI/I2C, etc.).
- Experience influencing design for testability and verification.
- Proven experience in troubleshooting and debugging.
- Experience with Formal Verification, hardware description languages (HDLs) such as Verilog/System Verilog).
- Experience with emulation and prototyping platforms (Veloce, HAPS).
- Experience collaborating with architecture and design teams on verification strategy.
The starting salary range posted for this position is $166,300.00 to $238,300.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.