Description
The Silicon One team at Cisco is looking for a DFT Verification Lead to join their team in San Jose, CA. This is a hybrid role with three days per week at Cisco's San Jose location.
The successful candidate will be responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture. They will collaborate with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
Key responsibilities include:
- Developing test plans based on complex design specifications
- Creating testbenches using System Verilog
- Debugging using DVE/Verdi
- Working with TCL, Python, or Perl
- Collaborating with cross-functional teams to drive high-quality DFT verification
The ideal candidate will have:
- Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
- Prior experience in test planning and testbench development
- Experience with UVM and advanced System Verilog knowledge
- Knowledge about JTAG protocol, scan architecture, MBIST and boundary scan
In terms of benefits, Cisco offers:
- Medical, dental, and vision insurance
- 401(k) plan with a Cisco matching contribution
- Paid parental leave
- Short and long-term disability coverage
- Basic life insurance
- Paid time away, including 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- Optional 10 paid days per full calendar year to volunteer
The starting salary range for this position is $186,900.00 to $267,700.00, and individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training.