Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You are a passionate and accomplished digital design engineer with an unyielding drive for excellence. You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems. With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.
Responsibilities:
- Lead and Drive all aspects of complete IP Design execution from start to end.
- Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.
- Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.
- Contributing as an individual designer and also lead other engineers in ,handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.
- Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.
- Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.
- Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.
- Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.
Requirements:
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.
- 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.
- Past experience of leading IP design projects, team.
- In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.
- Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.
- Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).
- Familiarity with scripting languages such as Perl or Shell,an advantage.
- Demonstrated ability to technically lead or mentor small teams of engineers.
Benefits:
- Comprehensive medical and healthcare plans that work for you and your family.
- Time away: In addition to company holidays, we have ETO and FTO Programs.
- Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- ESPP: Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
- Retirement Plans: Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.