SoC RTL Design - Sr Staff

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years building and signing off RTL that actually ships in silicon, not just passes simulation. The difference between a design that tapes out clean and one that comes back with a respin is usually a clock domain crossing someone missed or a constraint someone wrote too loosely, and you are the engineer who catches those things before they become problems.

Responsibilities

• Run RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SoC designs
• Develop timing constraints in SDC for synthesis and static timing analysis, ensuring constraints accurately reflect design intent and architecture
• Execute preliminary synthesis runs using Design Compiler or Fusion Compiler to validate RTL synthesizability, area, and timing feasibility before handoff
• Perform formal equivalence checking with Formality to verify RTL-to-gate consistency across design revisions and ECOs
• Integrate third-party and Synopsys IP into customer SoCs and subsystems, resolving integration issues related to clocking, reset, and interface protocols
• Create and modify RTL design blocks to meet customer-specific requirements, working within established design guidelines and delivery timelines
• Collaborate with verification, implementation, and architecture teams to close signoff issues and ensure RTL quality gates are met before tapeout

The Impact You Will Have

• Your signoff rigor directly reduces respin risk for customers building chips in advanced nodes where a single CDC bug can cost months and millions
• The constraints you write become the foundation for physical implementation teams to close timing, making or breaking their ability to meet PPA targets
• Your synthesis validation catches architectural mismatches early, preventing costly surprises downstream in place and route
• The IP integrations you deliver enable startups and tier-one customers to meet aggressive tapeout schedules with confidence in design quality
• Your expertise in static verification tools shapes internal methodology, raising the bar for what clean RTL means across the System Solutions Group
• The RTL you design and integrate becomes part of production SoCs powering AI, automotive, 5G, and IoT applications in the field
• Your work helps Synopsys customers tape out some of the most complex and challenging semiconductor designs in the industry

Requirements

• Bachelor's or Master's in Electronics Engineering, Electrical Engineering, or Computer Engineering with 8+ years of hands-on experience in RTL design and verification
• Proven experience performing static verification using Spyglass or equivalent tools for LINT, CDC, and RDC analysis on complex digital designs
• Strong working knowledge of synthesis tools such as Design Compiler or Fusion Compiler, including constraint development and synthesis quality checks
• Hands-on experience with Formality or equivalent formal verification tools for RTL-to-gate equivalence checking
• Solid conceptual understanding of clock domain crossing, reset domain crossing, and common design pitfalls that lead to metastability or functional failures
• Experience integrating IP blocks into subsystems or SoCs, including resolving interface, clocking, and protocol issues
• Familiarity with scripting in Tcl, Python, or Perl to automate checks, reporting, and design flows is a strong plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away: company holidays, ETO, and FTO Programs
• Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans: save for your future with our retirement plans that vary by region and country
• Competitive salaries