VC Formal Staff Application Engineer

We are seeking an experienced VC Formal Staff Application Engineer to work directly with customers deploying VC Formal across complex SoC and IP designs.

As a VC Formal Staff Application Engineer at Synopsys, you will lead technical deployment of VC Formal at customer sites, assessing their verification environments and recommending formal methodologies that fit their design challenges.

Key responsibilities include:

• Analyzing customer design blocks to identify candidates for formal property checking, sequential equivalence, connectivity checking, and formal coverage analysis
• Diagnosing root causes of tool performance issues and design complexity bottlenecks, then optimizing formal testbench modeling to achieve proof closure
• Developing and delivering technical training on VC Formal features, product updates, and formal verification best practices
• Working with Synopsys R&D teams to communicate customer priorities and technical requirements that influence the product roadmap

The impact you will have:

• Enabling customers to catch critical design bugs earlier, reducing costly respins and time to tapeout
• Driving measurable improvements in formal tool performance and proof convergence through optimized modeling
• Influencing the VC Formal product roadmap by translating customer pain points into actionable R&D priorities

Requirements:

• 4 to 8 years of hands-on experience applying formal verification in semiconductor design or verification roles
• Deep expertise in formal property checking, including writing assertions, constraints, and assumptions for complex digital designs
• Proven experience with sequential equivalence checking, formal coverage analysis, and connectivity checking methodologies
• Strong understanding of formal verification theory, including state space exploration, abstraction techniques, and proof convergence strategies

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.