Description
You are a seasoned Physical Design Staff Engineer looking to engineer the future with Synopsys, the leader in silicon to systems solutions. With years of experience in physical design under your belt, you understand the intricacies of timing closure, signoff readiness, and PPA optimization for advanced-node customer designs.
Your expertise spans developing and enhancing physical design methodologies and automation solutions using TCL, Python, Perl, or Pandas. You're adept at performing static timing analysis, clock-tree synthesis, and ECO implementation using industry-standard tools like PrimeTime, ICC2, Fusion Compiler, or Cadence Innovus.
As a Physical Design Staff Engineer at Synopsys, you will drive timing closure, signoff readiness, and PPA optimization for advanced-node customer designs. You will develop and enhance physical design methodologies and automation solutions to improve design quality, predictability, and team efficiency. Your responsibilities also include:
- Performing static timing analysis, clock-tree synthesis, and ECO implementation using tools like PrimeTime, ICC2, Fusion Compiler, or Cadence Innovus
- Analyzing design data and trends to identify bottlenecks, predict issues, and build flows that make the next tapeout smoother than the last
- Collaborating with cross-functional engineering teams including design, verification, and CAD to ensure successful silicon delivery
- Contributing to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve complex implementation challenges
- Troubleshooting complex physical design problems that do not have obvious answers, and developing scalable technical solutions that work across multiple projects
In this role, your methodologies and automation will directly reduce design cycle time and improve first-pass silicon success for Synopsys customers building chips at 3nm, 2nm, and beyond. Your contributions will shape how future tools and methodologies are developed at Synopsys.
To excel in this position, you need:
- A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
- 5+ years of hands-on experience with ASIC physical design, implementation, and timing closure across block, subsystem, or chip-level designs
- Deep working knowledge of static timing analysis, clock-tree synthesis, signoff flows, and ECO methodologies
- Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus
- Strong scripting and automation skills using TCL, Python, Perl, or similar languages to build flows and analyze data
- Experience with advanced-node semiconductor design at 7nm or below is a strong plus
- Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows is a plus
In return for your expertise, Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs.