The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Design Engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. As a Clocks team member, you will collaborate with other architects, ASIC designers and verification engineers to design high frequency and low power clocks. You should be able to engage with multiple teams and design the GPU clocks to satisfy all the architectural constraints. Responsibilities include: Collaborating with frontend design team to understand clocking requirements for the chip Working with backend teams to understand physical restrictions Architecting, designing and validating clocks RTL Running and enhancing in-house flow to guarantee good quality of clocks RTL and netlist Delivering clock information to SOC verification team, timing and DFT teams Using Perl/Python to improve productivity Collaborating with software and silicon solution team to debug GPU clock silicon bugs Requirements: BS or MS in EE or equivalent experience 2+ years of meaningful work experience Validated experience in RTL design (Verilog), verification and logic synthesis Strong coding skills in Perl or Python or other industry-standard scripting languages Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus Good understanding of backend flows and requirements is a plus DFT knowledge is a plus Experience in implementing on-chip clocking networks is desirable Excellent analytical and problem-solving skills Fluent English (both written and spoken) and excellent communication skills Good teamwork spirit, easy to cooperate with team members