# Digital Design Verification Engineer

**Company**: Synopsys
**Location**: Ottawa
**Work arrangement**: onsite
**Experience**: mid
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/ottawa/digital-design-verification-engineer-14733/44408/91320791920
**Canonical**: https://yubhub.co/jobs/job_fc83528d-25d

## Description

At Synopsys, we drive innovations that shape how we live and connect. Our technology is central to chip design, verification, and IP integration, empowering high-performance silicon chips and software content.

We are seeking a detail-focused engineer with strong digital design and verification skills to join our team. As a Digital Design Verification Engineer, you will be responsible for defining and tracking verification test plans, designing SystemVerilog testbenches using UVM, applying mixed-signal verification techniques, creating and analyzing functional coverage, writing SystemVerilog assertions, and debugging simulation failures.

You will ensure reliable, high-quality silicon products, accelerate development cycles, enhance product performance, drive innovation in verification methodologies, collaborate across teams, and influence best practices.

To be successful in this role, you will need a BSEE with at least 1 year of direct industry experience, strong digital design theory knowledge, experience with UVM and SystemVerilog, mixed-signal verification understanding, test plan and coverage analysis skills, and scripting experience (Perl, Python, Bash, Csh).

As a collaborative team player, you will be analytical, detail-oriented, quick to learn, and effective in communication.

You will join a dynamic team focused on reliable, innovative silicon solutions, working closely with design and product groups.

We offer a comprehensive range of health, wellness, and financial benefits, including competitive salaries, comprehensive medical and healthcare plans, time away programs, family support, ESPP, and retirement plans.

## Skills

### Required
- SystemVerilog
- UVM
- mixed-signal verification
- test plan and coverage analysis
- scripting (Perl, Python, Bash, Csh)