# Senior FPGA Engineer

**Company**: Astranis
**Location**: San Francisco
**Experience**: senior
**Job type**: full-time
**Salary**: $175,000-$240,000 USD
**Category**: Engineering
**Industry**: Technology
**Wikidata**: https://www.wikidata.org/wiki/Q96372482

**Apply**: https://job-boards.greenhouse.io/astranis/jobs/4017405006?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_f9cdf535-db2

## Description

Astranis builds advanced satellites for high orbits, expanding humanity's reach into the solar system.

As a Senior FPGA Engineer, you'll be responsible for the architecture, design, verification, and test of RTL designs for the FPGAs that go into the spacecraft and on the ground station.

Responsibilities:

- Design RTL for high-performance systems, including software-defined radios, avionics, and ground systems, for commercial and US Government projects

- Work with multiple FPGAs and toolchains

- Interface FPGAs with high-speed data converters, memories, MCUs

- Design, implement, and test radiation mitigation schemes on FPGA

- Collaborate closely with DSP/radio algorithm designers, embedded firmware, and software engineers

- Assist in recruiting, interviewing, and hiring additional teammates

Requirements:

- Bachelor of Science degree in electrical engineering, computer science, computer engineering, or equivalent

- 5+ years of experience

- Experience in designing, implementing, and testing high-throughput systems implemented on FPGAs

- Strong proficiency with Verilog/SystemVerilog for both synthesis and verification

- Familiarity with system-level estimates and implications of power, thermal, and real estate

Bonus skills:

- MS or PhD in computer engineering or equivalent

- Considerable expertise in at least one domain beyond just logic design

- Experience with Xilinx Ultrascale/Ultrascale+/Versal FPGA's, Vivado IDE, TCL, high-speed data converters, UVM, and DPI simulation methodologies

What we offer:

- Compensation package that includes equity and robust benefits

- Base pay: $175,000-$240,000 USD

- High-quality company-subsidized healthcare, disability and life insurance, 401(k) retirement planning, flexible PTO, and free on-site catered meals

## Skills

### Required
- FPGA design
- RTL design
- Verilog/SystemVerilog
- FPGA verification
- high-throughput systems
- power and thermal analysis

### Nice to have
- Xilinx Ultrascale/Ultrascale+/Versal FPGA's
- Vivado IDE
- TCL
- high-speed data converters
- UVM
- DPI simulation methodologies
- digital communication theory
- DVB-S2X modulation/demodulation
- FEC encoding/decoding

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Source: [Apply at job-boards.greenhouse.io](https://job-boards.greenhouse.io/astranis/jobs/4017405006?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)