# Silicon One Team Member **Company**: Cisco **Location**: San Jose, California **Experience**: senior **Job type**: full-time **Salary**: $125,700.00 - $203,100.00 **Category**: Engineering **Industry**: Technology **Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Power-Design-Engineer-II--Full-Time----United-States_2030409?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_f6b017d7-cf0 ## Description The Silicon One team at Cisco creates innovative hardware platforms central to the AI era, powering core Switching, Routing, and Wireless products for organizations globally. Your Impact: - Implement and optimize low-power design methodologies (clock gating, power gating, multi-Vt, dynamic voltage and frequency scaling, and UPF/CPF power intent). - Perform block- and full-chip-level power analysis and estimation using Synopsys PrimePower (PTPX) across various operating modes, PVT corners, and functional activity scenarios (VCD/FSDB/SAIF). - Collaborate closely with RTL design, architecture teams to identify power bottlenecks and guide RTL/micro-architectural power optimizations. - Achieve timing closure, signal integrity, and power targets across advanced process nodes (FinFET / GAA). - Develop and maintain automated design and analysis workflows using Python, TCL, and Perl. - Participate in post-silicon power and performance validation and correlation against pre-silicon PrimePower models. Minimum Qualifications: - Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelors + 2 years of relevant experience or Master’s degree program + 0 years of relevant experience. (Relevant fields include ASIC Design or Power Design.) - Strong familiarity with low-power design concepts and techniques (UPF/IEEE 1801, clock gating, multi-voltage domains, power switches, retention cells, leakage vs. dynamic power trade-offs). - Proficiency with hardware description languages (SystemVerilog / Verilog). - Scripting capability in TCL, Python, or Perl for EDA tool automation and data parsing. - Familiarity with Linux/Unix development environment Preferred Qualifications: - Direct experience running activity-driven power analysis using FSDB/VCD/SAIF waveforms generated from gate-level and RTL simulations - Experience with industry-standard EDA tools such as Synthesis & P&R: Synopsys Design Compiler, Fusion Compiler, IC Validator, or Cadence Innovus and Timing & Signoff: Synopsys Prime Time / Prime Time-SI, Prime Power, StarRC, Siemens Calibre. - Experience with power integrity / IR-drop / EM analysis tools (e.g., Ansys RedHawk, Voltus). - Understanding of sophisticated FinFET/GAA process node design rules and low-power library architectures. - Excellent problem-solving, partnership, and communication skills within multi-functional teams Benefits: - Medical, dental and vision insurance - 401(k) plan with a Cisco matching contribution - Paid parental leave - Short and long-term disability coverage - Basic life insurance - Paid time away (10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees, 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness) - Optional 10 paid days per full calendar year to volunteer Salary Range: $125,700.00 - $203,100.00 (New York City Metro Area) $111,700.00 - $180,800.00 (Non-Metro New York state & Washington state) ## Skills ### Required - ASIC Design - Power Design - Low-power design - Synopsys PrimePower - Python - TCL - Perl - SystemVerilog - Verilog - Linux/Unix ### Nice to have - FSDB/VCD/SAIF waveforms - EDA tools - Power integrity / IR-drop / EM analysis tools - FinFET/GAA process node design rules --- Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Power-Design-Engineer-II--Full-Time----United-States_2030409?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)