# Senior Signal & Power Integrity Engineer

**Company**: NVIDIA
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Signal-and-Power-Integrity-Engineer---Hardware_JR2027748?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_f63493c1-535

## Description

We are seeking a Senior Signal & Power Integrity Engineer to join our dynamic team. You will work on crafting creative Signal Integrity solutions to complex system design problems.

Responsibilities:

- Work on system-level signal integrity simulations of high-speed NVlinks 200Gbs+, USB-4, PCIe5, GDDR6, LP5X

- Model vias, connectors, sockets and various system components in 3D EM tools

- Design and optimize Power Delivery Network (PDN) across packages and PCBs

- Constantly improve SI/PI models through lab measurements

- Automate simulation, gather data, analyze and visualize using JMP, MATLAB or similar tools

- Work in a dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit

Requirements:

- BS/MS in Electrical Engineering or equivalent experience

- 3+ years of industry experience

- Experience with SI/PI work on one or more signaling standards like PCI express, USB, SATA, HDMI, HBM, DDR5, GDDR6, LPDDR5X

- Hands-on use of 3-D modeling tools like ANSYS HFSS/Q3D and 2.5-D with ANSYS SIWAVE or similar

- Experience with PDN evaluation using layout extraction tools for packages and PCBs and spice-based time domain simulations

- Background with system-level timing or loss budget including silicon, package and board impairments

- Familiarity with use of VNA, TDR, DSO, ParBERT and use of applications like JMP, Matlab will be a plus

Preferred qualifications:

- Expertise in one or more of the high-speed interface SI/PI design on any industry standard system platforms

- Experience with lab measurements, debugging, SI lab correlation using oscilloscope/ spectrum analyzer/ VNA

- Knowledge of circuit design, board/pkg component design, link architecture, timing budget methodologies

Benefits:

- Base salary range: 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4

- Equity and benefits

## Skills

### Required
- Signal Integrity
- Power Integrity
- Electrical Engineering
- 3D EM tools
- ANSYS HFSS/Q3D
- PDN evaluation
- layout extraction tools
- spice-based time domain simulations

### Nice to have
- high-speed interface SI/PI design
- lab measurements
- debugging
- SI lab correlation
- circuit design
- board/pkg component design
- link architecture
- timing budget methodologies

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Signal-and-Power-Integrity-Engineer---Hardware_JR2027748?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)