# Staff Applications Engineer, Synthesis and Formal Verification

**Company**: Synopsys
**Location**: Sunnyvale, California
**Experience**: staff
**Job type**: full-time
**Salary**: $129,000-$193,000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/sunnyvale/staff-applications-engineer-synthesis-and-formal-verification/44408/102308197952?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_f42d1e25-9eb

## Description

You will work as a Staff Applications Engineer, Synthesis and Formal Verification at Synopsys, Sunnyvale, California, United States. The base salary range for this position is $129,000-$193,000.

You have spent years in the trenches of ASIC design, and you know that the cleanest RTL and the best synthesis settings mean nothing if the customer cannot actually use them. You have debugged enough late-stage timing failures to recognize the synthesis decision that caused it three weeks earlier, and you care enough to prevent that from happening again.

### Responsibilities

- Own technical relationships with customer RTL, synthesis, formal verification, and physical design teams from flow evaluation through tapeout, serving as their trusted technical partner for Synopsys synthesis and equivalence checking products

- Debug complex synthesis and Formality issues reported by customers, reproduce problems in your own environment when possible, isolate root causes, and deliver clear recommendations or escalate to R&D with well-documented test cases

- Guide customers on RTL-to-netlist methodology using Fusion Compiler, Design Compiler, RTL Architect, and Formality, including advice on hierarchy, datapath optimization, physical-aware synthesis, clock gating, multi-bit registers, and handoff to place-and-route

- Analyze synthesis results, timing reports, constraint files, library characterization, and PPA outcomes to explain design behavior, identify optimization opportunities, and improve correlation with downstream implementation

- Create and maintain reusable scripts, reference flows, application notes, debug guides, and training materials that scale across customer programs and can be shared with global applications teams

- Translate recurring customer challenges and feature requests into clear use cases and product feedback for Synopsys R&D, and validate fixes and enhancements in real customer contexts

- Support technical evaluations, benchmarks, design reviews, and adoption of new synthesis and formal verification technologies across customer design teams

### The Impact You Will Have

- Customers will ship complex SoCs on schedule because you helped them resolve synthesis and equivalence checking issues that would have blocked tapeout

- Design teams will achieve better power, performance, and area outcomes because you identified RTL, constraint, or methodology improvements they could not see on their own

- Synopsys products will become more robust and easier to deploy because you brought field observations back to R&D as reproducible test cases and actionable feature requests

- Customer synthesis flows will scale and stabilize across programs because you built reference methodologies, scripts, and documentation that teams can reuse without starting from scratch

- Engineers at customer sites will trust Synopsys as a technical partner, not just a vendor, because you showed up during the hard problems and helped them solve it

- Your colleagues across global applications, support, and product engineering teams will benefit from the knowledge you share, the materials you create, and the mentorship you provide

- Synopsys will win competitive evaluations and expand deployments because customers see the value you deliver during technical engagements and benchmarks

### Requirements

- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience in ASIC design or EDA applications

- 5 or more years of hands-on experience in ASIC or SoC design, logic synthesis, formal equivalence checking, or EDA applications engineering, with at least one production design cycle or tapeout under your belt

- Strong working knowledge of Verilog or SystemVerilog RTL, logic synthesis fundamentals, timing constraints (SDC), standard-cell libraries, and RTL-to-netlist design flows

- Practical experience with formal equivalence checking tools, including the ability to set up comparisons, investigate setup issues, and analyze proof failures or inconclusive results

- Proficiency with Tcl scripting and Linux command-line environments, you can write or modify scripts to automate flow setup, parse reports, and accelerate debug

- Direct experience with Synopsys Design Compiler, Fusion Compiler, RTL Architect, or Formality is a strong plus, as is familiarity with static timing analysis tools like PrimeTime

- Experience with UPF, low-power design, hierarchical SoCs, advanced process nodes, or physical-aware synthesis is valuable but not required

## Skills

### Required
- ASIC design
- EDA applications
- Logic synthesis
- Formal equivalence checking
- Verilog
- SystemVerilog
- Tcl scripting
- Linux command-line environments

### Nice to have
- Synopsys Design Compiler
- Fusion Compiler
- RTL Architect
- Formality
- PrimeTime
- UPF
- Low-power design
- Hierarchical SoCs
- Physical-aware synthesis

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/sunnyvale/staff-applications-engineer-synthesis-and-formal-verification/44408/102308197952?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)