# ASIC Digital Design, Sr Staff Engineer-19314 **Company**: Synopsys **Location**: Markham, ON **Experience**: senior **Salary**: $122000-$183000 **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/markham/asic-digital-design-sr-staff-engineer-19314/44408/102599718368?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_eed5c132-27b ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. As a motivated and innovative ASIC digital verification engineer, you will be part of a highly experienced mixed-signal design team. You will be involved in verifying current and next-generation Backplane Ethernet, PCIe, SATA, and USB SERDES products. The position offers an excellent opportunity to work with an expert team of digital and mixed-signal engineers responsible for delivering high-end mixed-signal designs. **Responsibilities** - Creating and updating test plans and test cases - Writing modular constrained-random/coverage driven Verilog, SystemVerilog, and UVM/VMM testbenches - Writing SystemVerilog assertions - Monitoring simulation regressions and debugging RTL and Gate level simulation failures - Writing functional coverage and performing functional/code/assertion coverage analysis - Tracking/Reporting issues in Jira and documenting in Confluence **Requirements** - BS/MS in Electronics / Electrical Engineering or related fields with 8+ years of industry experience with digital verification methodology such as VMM/UVM - Solid experience in writing testcases in Verilog and System Verilog - Solid experience in debugging complex testbench and design-related issues - Knowledge of high-speed digital & mixed-signal design - Solid understanding of digital circuit design - Basic understanding of C/C++ and RISC processors - Familiarity with scripting languages (Python or Perl) - Self-learner/independent, good organization and communication skills **The Impact You Will Have** - Catch critical bugs before tapeout that would otherwise cost months of schedule and significant silicon respins - Enable faster time-to-market for high-speed SerDes IP used in data center, automotive, and consumer products worldwide - Build reusable verification infrastructure that accelerates future product development and reduces verification cycle time - Improve coverage closure rates and regression stability, giving the team confidence to tape out on schedule - Mentor and influence verification methodology across the IP team, raising the bar for testbench quality and debug efficiency - Contribute to the success of mixed-signal products that power connectivity in millions of devices - Help shape verification strategy and tooling decisions that affect how the entire team works **Rewards and Benefits** - Comprehensive medical and healthcare plans that work for you and your family - Time away: company holidays, ETO, and FTO Programs - Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more - ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back - Retirement plans: save for your future with our retirement plans that vary by region and country - Competitive salaries ## Skills ### Required - Verilog - SystemVerilog - UVM/VMM - digital verification - mixed-signal design - C/C++ - RISC processors - Python - Perl ### Nice to have - System Verilog Assertions - formal verification --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/markham/asic-digital-design-sr-staff-engineer-19314/44408/102599718368?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)