# Senior Digital Design Verification Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Digital-Design-Verification-Engineer---Hardware_JR2028075?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/senior-digital-design-verification-engineer-edac2550-011/

## Description

As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify the design and implementation of cutting-edge SerDes IPs, enabling gaming, artificial intelligence, deep learning, and autonomous driving.

**Responsibilities:**

- Develop and execute verification plans for SerDes digital designs, golden models, and microarchitecture using SystemVerilog/UVM, simulation, and hardware emulation.

- Develop, bring up, and debug SerDes verification environments on Cadence Palladium, including preparing designs and testbenches for emulation and running long-duration system scenarios.

- Write and maintain C/C++ reference models, stimulus generators, checkers, and test code to support simulation and emulation.

- Investigate failures across RTL, verification infrastructure, C/C++ models, and RNM models, and collaborate with designers to resolve issues.

- Work with architects, digital and analog designers, and pre- and post-silicon verification teams to define verification scope, close coverage, and deliver high-quality IP on schedule.

**Requirements:**

- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.

- At least 5 years of relevant design verification experience at the unit, subsystem, or SoC level.

- Hands-on experience with Cadence Palladium or a comparable hardware emulation platform.

- Strong C/C++ programming skills, with experience developing verification models, test infrastructure, or hardware validation tests.

- Strong SystemVerilog skills and experience building verification environments using UVM.

- Experience with constrained-random stimulus, functional coverage, assertions, and coverage closure.

- Strong debugging and analytical skills, including isolating emulation failures and reproducing issues in simulation.

**Preferred Qualifications:**

- Direct experience bringing up and debugging SerDes IP or subsystems on Cadence Palladium.

- Experience adapting UVM testbenches, C/C++ models, and mixed-signal behavioral models for efficient emulation.

- Experience developing SerDes RNM models and correlating their behavior with analog simulation results or silicon measurements.

- Understanding of SerDes architectures, mixed-signal interfaces, calibration, adaptation, and link training.

- Expertise in high-speed protocols such as PCI Express, USB, or SATA.

You will also be eligible for equity and benefits.

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## Skills

### Required
- SystemVerilog
- UVM
- C/C++
- Cadence Palladium
- hardware emulation
- verification models

### Nice to have
- SerDes IP
- mixed-signal behavioral models
- PCI Express
- USB
- SATA

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Digital-Design-Verification-Engineer---Hardware_JR2028075?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)