# Serdes IP Design Engineer

**Company**: Synopsys
**Location**: Wuhan, Hubei
**Experience**: mid
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/wuhan/serdes-ip-design-engineer/44408/102946018752?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/serdes-ip-design-engineer-ed4f1fa7-905/

## Description

We are seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow to join our team of experienced mixed-signal design and verification engineers. As a Serdes IP Design Engineer at Synopsys, you will work on high-speed SERDES products such as USB4.0v2, USB4.0, PCIe4.0, Ethernet, DP2.0, HDMI2.1, and MIPI MPHY products (up to 40 Gbps).

Your responsibilities will include:

- Designing and verifying high-speed SERDES and data recovery circuits

- Writing block-level test-cases, including constrained directed random tests

- Working with Verilog and VCS, and having good knowledge of back-end synthesis tools DC/PT

- Understanding digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints, and flows

- Scripting experience in Shell, Perl, Python, and TCL is a plus

- Good communication skills for interacting with different design groups and customer support teams

We offer comprehensive benefits, including health and wellness programs, time away, family support, ESPP, retirement plans, and competitive salaries.

If you have a solid theoretical and practical background in high-speed SERDES and data recovery circuits, and are looking for a challenging role with opportunities for growth and development, we encourage you to apply.

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## Skills

### Required
- ASIC development flow
- digital design and verification
- Verilog
- VCS
- DC/PT
- DFT insertion
- Synthesis constraints and flows
- Shell
- Perl
- Python
- TCL

### Nice to have
- RTL coding
- modeling of analog blocks
- writing complex system-level test-benches in Verilog
- defining synthesis design constraints
- resolving STA issues
- gate-level simulation failures
- defining Clock/Reset domain crossing design constraints
- evaluating violations using CDC/RDC tools

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/wuhan/serdes-ip-design-engineer/44408/102946018752?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)