# Layout Design, Staff Engineer

**Company**: Synopsys
**Location**: Noida, Uttar Pradesh
**Experience**: staff
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/noida/layout-design-staff-engineer/44408/101119414160?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_ea47c380-e8d

## Description

## Overview

We're looking for a Layout Design, Staff Engineer at Synopsys, a leading provider of engineering solutions from silicon to systems.

## Job Description

As a Layout Design, Staff Engineer, you will design and develop cutting-edge semiconductor solutions, focusing on custom memory layout, particularly for SRAM, Register Files, ROM, and related memory compiler IP blocks.

### Key Responsibilities

- Design and own custom layouts for SRAM, Register Files, ROM, and related memory compiler IP blocks from floorplan through final signoff

- Execute and close DRC, LVS, ERC, antenna, density, and reliability checks using Virtuoso and physical verification tools

- Drive technology node migrations for memory compilers, resolving layout and verification issues that emerge with new process rules

- Collaborate directly with circuit designers to ensure schematic-layout correlation, device matching, symmetry, and design intent are preserved

- Develop and refine layout methodologies, automation scripts in Tcl, Perl, or Python, and best practices that improve team efficiency and design quality

- Review layouts created by junior engineers, provide technical guidance, and mentor on complex layout challenges

- Support customer-specific memory customization projects, working through optimization requests and delivering production-ready IP

### What You'll Need

- Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field

- 8 to 10 years of hands-on experience in custom memory layout design, specifically SRAM, Register Files, ROM, or memory compiler development

- Strong proficiency with custom layout tools such as Cadence Virtuoso or equivalent platforms

- Demonstrated expertise in DRC/LVS closure, device matching and symmetry, and analog/custom layout techniques

- Deep understanding of CMOS layout fundamentals, memory architecture, and FinFET technology nodes

- Experience with parasitic extraction and physical verification flows, and the ability to interpret and act on results

- Familiarity with scripting in Tcl, Perl, or Python for layout automation is a strong plus

## Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs, including:

- Comprehensive medical and healthcare plans

- Time away programs

- Family support, including maternity and paternity leave

- ESPP (Employee Stock Purchase Plan)

- Retirement plans

- Competitive salaries

## Skills

### Required
- custom memory layout design
- Cadence Virtuoso
- DRC/LVS closure
- device matching and symmetry
- analog/custom layout techniques
- CMOS layout fundamentals
- memory architecture
- FinFET technology nodes
- parasitic extraction
- physical verification flows
- Tcl
- Perl
- Python

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/noida/layout-design-staff-engineer/44408/101119414160?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)