# Senior Manager, ASIC Digital Design

**Company**: Synopsys
**Location**: Kanata
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/kanata/senior-manager-asic-digital-design/44408/93286401664
**Canonical**: https://yubhub.co/jobs/job_e9f309b8-35d

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

As a Senior Manager, ASIC Digital Design, you will lead a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions. You will collaborate with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.

Key responsibilities include:

* Leading a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions
* Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products
* Planning, scheduling, and driving all phases of SERDES PHY IP design, from specification through productization and customer support
* Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles
* Mentoring and developing team members, fostering technical growth, and a culture of innovation
* Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges

The impact you will have includes delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency, empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications, and driving technical innovation that strengthens Synopsys' leadership in the mixed-signal IP market.

## Skills

### Required
- Verilog
- System Verilog
- front-end design flows
- linting
- synthesis
- static timing analysis
- cross-domain clocking
- DFT
- power optimization

### Nice to have
- DDR memory
- DDR PHY architecture