# Signal and Power Integrity Engineer

**Company**: Cisco
**Location**: San Jose, California
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $125,700.00 - $176,600.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Packaging-SI-PI-Engineer--Hybrid-_2030802?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/signal-and-power-integrity-engineer-e8f0cadc-2ff/

## Description

We are seeking a qualified Signal and Power Integrity Engineer to help us develop our next generation ASIC packaging. You will define, design, and verify ASIC packaging to be deployed in a range of Cisco platforms.

Responsibilities:

- Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.

- Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.

- Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.

- Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.

Minimum Qualifications:

- Bachelors + 2 years of related experience, or Masters + 0 years of related experience.

- Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis.

- Experience in pre- and post-layout signal and power integrity (SI/PI) analysis.

- Experience with simulation using industry-standard EDA tools (e.g., Cadence Sigrity, Ansys HFSS, Keysight ADS).

- Experience planning and executing comprehensive SI/PI measurements and laboratory characterization.

Preferred Qualifications:

- Experience with articulating ideas and technical concepts to diverse audiences, both verbally and in writing.

- Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.

- Experience with die-to-die interfaces (UCIe or proprietary).

- Experience with advanced packaging (CoWoS, EMIB, interposer-based designs).

Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds.

Benefits:

- Medical, dental, and vision insurance

- 401(k) plan with a Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- Paid time away (vacation, holidays, sick time)

- Optional 10 paid days per full calendar year to volunteer

Salary Range: $125,700.00 - $176,600.00

For more fresh new jobs, check out [yubhub.co](https://yubhub.co/).

## Skills

### Required
- high-speed design
- signal integrity
- power integrity
- EDA tools
- SI/PI simulation
- measurement planning
- execution

### Nice to have
- high-bandwidth memory
- die-to-die interfaces
- advanced packaging
- articulating technical concepts

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Packaging-SI-PI-Engineer--Hybrid-_2030802?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)