# Senior IC Packaging Design Engineer

**Company**: NVIDIA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Yokneam/Senior-Package-Layout-Engineer_JR2025722?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_e866cceb-a1e

## Description

NVIDIA's IC Packaging design team is seeking a Senior IC Packaging Design Engineer to focus on designing state-of-the-art high-speed interconnect systems for supercomputers and datacenters.

The successful candidate will collaborate with the Technical Package Lead and other design teams to develop complex, detailed layouts of IC substrates for NVIDIA products.

Responsibilities:

- Implement high-speed and PDN design for ASIC packages as part of the IC Packaging design team

- Develop symbols, pad stacks, and perform substrate package routing, placement, stack-up, reference plane, and power distribution using Cadence APD (Allegro) or SiP tools

- Optimize package pin-out incorporating system-level trade-offs of pin assignments

- Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations

- Collaborate with SI/PI/HW design teams and product teams

- Plan, ensure stakeholder management, and lead projects from start to finish

Requirements:

- B.Sc. Electrical Engineering or an Electrical Practical Engineer certificate or equivalent experience

- 5+ years of hands-on experience in package/PCB layout and routing, including high-speed design signal integrity practices

- Experience in substrate layout of wire bond and flip chip packages

- Knowledge of substrates or board manufacturing processes

- Significant background with Cadence Virtuoso and APD (Allegro) or SiP and/or other PCB layout tools

Preferred skills:

- Knowledge of Ansys (SIwave, HFSS) or Cadence (Sigrity, PowerSI) simulation tools

- Familiarity with Skill language (Cadence) and basic parsing abilities (Python/Perl/Shell-scripting)

## Skills

### Required
- Cadence APD (Allegro)
- SiP tools
- Electrical Engineering
- high-speed design
- signal integrity
- PCB layout
- substrate layout

### Nice to have
- Ansys (SIwave, HFSS)
- Cadence (Sigrity, PowerSI)
- Skill language (Cadence)
- Python
- Perl
- Shell-scripting

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Yokneam/Senior-Package-Layout-Engineer_JR2025722?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)