# Leader/Manager, ASIC Design Verification Engineering

**Company**: Cisco
**Location**: Bangalore, India
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Bangalore-India/Leader-Manager--ASIC-Design-Verification-Engineering----Verilog--UVM--TestBench--Technical-Leadership--Hardware-Emulation--SOC----Exp---15---years_2025084?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_e7788ef9-114

## Description

Join the Cisco SiliconOne team as an ASIC Engineering Leader, responsible for leading ASIC design verification engineering efforts. You'll craft Enterprise and Service Provider solutions, working with complex chips and getting full exposure to all aspects of systems and applications built.

Key Responsibilities:

- Lead ASIC engineering teams to deliver high-performance, high-quality ASICs for Cisco's product platforms.

- Define and verify ASICs and subsystems to ensure alignment with quality requirements.

- Drive collaboration across functions to achieve high-volume production with uncompromised quality.

- Collaborate with design and hardware teams to verify ASICs in simulation, emulation, and during bring-up.

- Develop and enhance UVM/System Verilog testbenches, focusing on reuse.

- Define new DV methodologies or enhance existing ones.

- Analyse architecture, identify problems, and propose solutions.

- Execute end-to-end verification of design blocks, integrate with full chip teams, and support testing.

- Generate, review, plan, and execute test plans, meeting ASIC group criteria.

- Develop emulation infrastructure using C/C++ for UVM-based verification environments.

- Perform gate-level simulation, SDF back-annotation, and code coverage analysis.

- Participate in all ASIC development phases, including RTL verification, emulation, and post-silicon validation.

- Recommend best practices, suggest innovative solutions, and drive design verification solutions.

- Lead and mentor junior engineers, focusing on efficiency, quality, and reusability.

Minimum Qualifications:

- 15+ years of hands-on experience in large-scale, high-performance ASIC design.

- Led a design team for 5+ years.

- Experience developing UVM-based infrastructure from scratch in multiple projects.

- Ability to handle complex features independently and work in a fast-paced environment.

- Strong teamwork and leadership skills.

- Proficient in C, C++, and debugging skills.

- Experienced in system debug, SW/HW bring-up, and silicon validation.

- Familiarity with hardware emulation platforms and tools.

Preferred Qualifications:

- Experience in DV methodology and definition of high-scale, high-performance ASICs.

- Planning overall DV architecture strategy and defining requirements.

- Conducting test plan reviews and leading complex debugs.

- Valid experience in flow automation and establishing guidelines.

- Mentoring senior resources in DV and DV methodologies.

- Excellent communication and leadership skills.

## Skills

### Required
- ASIC design verification
- System Verilog
- UVM
- C++
- Hardware Emulation
- SOC
- Technical Leadership

### Nice to have
- DV methodology
- Test plan reviews
- Flow automation
- Mentoring

---

Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Bangalore-India/Leader-Manager--ASIC-Design-Verification-Engineering----Verilog--UVM--TestBench--Technical-Leadership--Hardware-Emulation--SOC----Exp---15---years_2025084?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)