# SOC Engineering, Staff Engineer (Physical Design) **Company**: Synopsys **Location**: Da Nang **Experience**: staff **Job type**: employee **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/da-nang/soc-engineering-staff-engineer-physical-design/44408/97596948784?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_e72e2a53-ade ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You have spent years turning RTL into silicon that actually works at the edge of what is physically possible. Not just meeting timing, actually closing complex die-to-die interfaces where a few picoseconds matter and where signal integrity is not a checkbox but the difference between a working chip and a $10M re-spin. ### Responsibilities - Own RTL-to-GDSII physical implementation for UCIe IP blocks, driving synthesis, floorplanning, power grid architecture, placement, clock tree synthesis, routing, and sign-off closure at 7nm, 5nm, or 3nm - Close timing across multiple PVT corners and operating modes, optimizing for the latency and bandwidth demands of high-speed die-to-die interfaces - Execute physical and electrical verification using Synopsys IC Validator, resolving DRC, LVS, ERC violations and mitigating electromigration, IR-drop, and signal integrity issues - Design and validate bump and pad ring patterns specific to die-to-die architectures, coordinating with package teams on complex routing constraints - Build and maintain automation scripts in Python, Tcl, and Perl to streamline back-end flows and eliminate bottlenecks - Prepare and deliver tape-out packages including GDSII databases, foundry checklists, and design documentation that meet sign-off requirements ### The Impact You Will Have - Enable Synopsys to deliver UCIe IP that meets the most aggressive performance and power targets in the industry, directly influencing chiplet adoption across AI, HPC, and data center markets - Reduce tape-out cycle time by identifying and fixing physical design issues early, preventing costly re-spins and keeping customer programs on schedule - Set the standard for physical design quality on advanced nodes, creating methodologies and flows that other teams across Synopsys will adopt - Solve die-to-die interface challenges that have no textbook answers, contributing technical solutions that become part of the next generation of IP offerings - Improve design predictability by building automation that catches timing, power, and signal integrity issues before they reach verification or silicon ### Requirements - Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field - 3 to 10+ years of hands-on ASIC physical design experience with proven RTL-to-GDSII ownership, ideally including tape-outs at 7nm, 5nm, or 3nm - Deep technical expertise in die-to-die interfaces such as UCIe, HBM, or high-speed DDR, including the timing, power, and signal integrity challenges unique to chiplet architectures - Strong proficiency with Synopsys physical design tools including IC Compiler II or Fusion Compiler, PrimeTime for timing sign-off, and IC Validator for physical verification - Advanced scripting skills in Tcl, Python, or Shell, with a track record of automating flows and solving complex design problems programmatically ### Benefits - Comprehensive medical and healthcare plans that work for you and your family - Time away: company holidays, ETO, and FTO Programs - Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more - ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back - Retirement plans: save for your future with our retirement plans that vary by region and country - Competitive salaries ## Skills ### Required - RTL-to-GDSII physical implementation - die-to-die interfaces - Synopsys physical design tools - Python - Tcl - Perl --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/da-nang/soc-engineering-staff-engineer-physical-design/44408/97596948784?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)