# Senior SRAM Circuit Design Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-SRAM-Circuit-Design-Engineer_JR2020272?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_e52ededb-ec7

## Description

NVIDIA's Digital IP (DIP) group is seeking a skilled Senior SRAM Circuit Design Engineer to develop sophisticated SRAM compilers used extensively by SOC design partners.

The successful candidate will be responsible for:

- Embedded SRAM design: transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.

- SRAM compiler development: envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.

- Advanced development: exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.

- Guiding SOC design, silicon test, and productization efforts: collaborating with SOC design partners to help them achieve their overall performance and cost goals, guiding the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.

Requirements:

- BSEE minimum (or equivalent experience), MSEE or PhD preferred.

- 8+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET and nanosheet processes.

- Prior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits such as self-timed logic and sense-amplifiers.

- Familiarity with Cadence Virtuoso schematic and layout capture tools.

- Proven track record of delivering silicon IP into production.

Preferred qualifications:

- Self-motivation, attention to detail, and good written, verbal, and presentation skills.

- Experience with AI coding and analysis tools such as Codex and Claude Code.

- Silicon testing/debug experience.

NVIDIA offers highly competitive salaries and a comprehensive benefits package.

## Skills

### Required
- SRAM design
- digital circuit design
- layout
- validation
- Cadence Virtuoso

### Nice to have
- AI coding
- Codex
- Claude Code
- silicon testing/debug

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-SRAM-Circuit-Design-Engineer_JR2020272?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)