# Signal and Power Integrity Technical Lead

**Company**: Cisco
**Location**: San Jose, CA
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: $186,900.00 to $267,700.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Hardware-ASIC-Packaging-SI-PI-Simulation-and-Design-Lead--Remote-_2028581?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_e40a18b7-8ed

## Description

We are seeking a highly qualified Signal and Power Integrity Technical Lead to help us develop our next generation ASIC packaging. You will define, design, and verify ASIC packaging to be deployed in a range of Cisco platforms.

Responsibilities:

- Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.

- Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.

- Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.

- Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.

- Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.

- Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.

- Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.

- Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.

Minimum Qualifications:

- Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience.

- High-Speed Design & Theory: Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.

- SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.

- Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.

- Circuit Analysis: Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.

Preferred Qualifications:

- Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.

- Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.

- Experience with die-to-die interfaces (UCIe or proprietary).

- Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.

- Experience with Vector Network Analysis.

- Experience with IBIS.

Benefits:

- Medical, dental, and vision insurance

- 401(k) plan with Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- Paid time away (vacation, holidays, sick time)

- Opportunities for professional growth and development

## Skills

### Required
- High-Speed Design
- Signal Integrity
- Power Integrity
- ASIC design
- EDA tools

### Nice to have
- High-bandwidth memory
- Die-to-die interfaces
- Advanced packaging
- Vector Network Analysis
- IBIS

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Hardware-ASIC-Packaging-SI-PI-Simulation-and-Design-Lead--Remote-_2028581?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)