# ASIC Floorplan Design Engineer - New College Grad 2026

**Company**: NVIDIA
**Location**: Santa Clara
**Work arrangement**: onsite
**Experience**: entry
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Floorplan-Design-Engineer---New-College-Grad-2026_JR2012971?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_dfec4a83-988

## Description

We are seeking a talented ASIC Floorplan Engineer to design and implement the world's leading SoCs and GPUs. This position offers you a unique opportunity to craft and influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic technology-focused company.

Your primary responsibilities will include:

- Developing and optimizing floorplans during early chip development with architects, design leads, physical design leads, and package leads.

- Driving the area review process and collaborating with the ASIC design team to identify area, interconnect, and floorplan improvement opportunities.

- Solving timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.

- Building tools and improving existing infrastructure to optimize chip area and speed of execution.

To be successful in this role, you will need:

- A Master's degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.

- A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.

- Experience in Verilog, System Verilog, or similar HVL.

- Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R, and timing closure.

- Strong communication and interpersonal skills and the ability to work as a great teammate.

- Python, Perl, and C/C++ programming language experience.

If you have experience in driving development of large-scale ASIC floorplan, it's a huge plus.

## Skills

### Required
- Verilog
- System Verilog
- HVL
- CAD
- Physical design methodologies
- Chip floorplan
- Power/clock distribution
- Packaging
- P&R
- Timing closure
- Python
- Perl
- C/C++

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Floorplan-Design-Engineer---New-College-Grad-2026_JR2012971?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)