# Applications Engineering, Sr Supervisor( Verification Tools)

**Company**: Synopsys
**Location**: Ho Chi Minh City, Ho Chi Minh
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/ho-chi-minh-city/applications-engineering-sr-supervisor-verification-tools/44408/101580799696?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_dfab890a-87e

## Description

We are seeking an experienced Applications Engineering, Sr Supervisor (Verification Tools) to provide advanced technical support for EDA Design & Verifications tools, addressing complex customer issues and ensuring customer satisfaction.

Responsibilities:

- Provide advanced technical support for EDA Design & Verifications tools (VCS, Verdi, Spyglass, Certitude, Z01X..)

- Take ownership of tool migrations, bring up verification environments, and Verification IPs

- Collaborate with worldwide Application Engineers, R&D teams, and Customers to understand requirements, address escalations, and ensure successful adoption of solutions and tool development

- Develop and share technical documentation, lead knowledge transfer, and mentor junior team members

- Lead the application engineers to technical campaigns and build trust with customers

Requirements:

- 3+ years of Design and Verification or Application Engineer experience

- Leading experience in Design and Verification, with strong skills in Verilog, UVM, System Verilog, VHDL, and UPF

- Experience leading and managing a team of Application Engineers

- Strong expertise in Design and Verification methodologies, Standard protocol, and Verification IPs

- Excellent communication skills in English

- Passion for using new tools and features, as well as AI-related tools

- Ability to manage relationships with customers and internal stakeholders

## Skills

### Required
- Verilog
- UVM
- System Verilog
- VHDL
- UPF
- Design and Verification methodologies
- Standard protocol
- Verification IPs

### Nice to have
- AI tool related

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/ho-chi-minh-city/applications-engineering-sr-supervisor-verification-tools/44408/101580799696?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)