# ASIC Digital Design, Sr Staff Engineer **Company**: Synopsys **Location**: Dublin, Leinster **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/dublin/asic-digital-design-sr-staff-engineer/44408/96919787104?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_df5b48a1-d5c ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You have spent years building digital IP that has to meet ISO 26262 ASIL D, not just pass functional verification. You know the difference between a controller that works in simulation and one that survives FMEDA, DFMEA, and real-world automotive stress, and you have debugged enough corner cases to know where those gaps usually hide. You think in RTL, but you also think in safety mechanisms, fault injections, and what it takes to qualify hardware for a car that cannot fail. **Responsibilities** - Design and own RTL for automotive digital IP blocks, with a focus on PCIe, DDR, or UCIe controllers that meet ISO 26262 functional safety requirements - Lead RTL coding, lint and CDC analysis, synthesis optimization, and debug across complex IP subsystems - Work closely with verification teams to define Verification IP scope, identify feature coverage gaps, and ensure controllers are fully validated before tapeout - Drive safety qualification activities including DFMEA, FMEDA, and DFA for IP targeting ASIL D - Mentor and guide engineering teams through design flows, coding standards, and best practices for synthesizable Verilog and System Verilog - Apply and evaluate AI-driven design tools and methodologies to improve design quality and automation **Requirements** - Bachelor's degree with 8+ years or Master's degree with 6+ years of relevant experience in Automotive SoCs or Digital IPs - Proven IP-level experience with protocols like PCIe, DDR, or UCIe, with PCIe experience strongly preferred - Demonstrated ability to work as an individual contributor while mentoring and leading engineering teams through RTL coding, lint/CDC analysis, synthesis, and debug - Experience qualifying embedded hardware systems to ISO 26262 ASIL levels up to ASIL D, and working with DFMEA, FMEDA, and DFA - In-depth experience writing synthesizable Verilog/System Verilog for ASIC design and simulation tools - Strong command of ASIC design flows, including lint, CDC, synthesis, Static Timing Analysis, and formal verification **Benefits** - Comprehensive medical and healthcare plans that work for you and your family - Time away programs, including ETO and FTO - Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance - ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back - Retirement plans that vary by region and country - Competitive salaries ## Skills ### Required - RTL development - ISO 26262 - PCIe - DDR - UCIe - Verilog - System Verilog - ASIC design - lint - CDC analysis - synthesis optimization ### Nice to have - PCIe experience --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/dublin/asic-digital-design-sr-staff-engineer/44408/96919787104?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)