# IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer

**Company**: Synopsys
**Location**: Beijing
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/beijing/ip-pcie-cxl-usb-dp-subsystem-design-implementation-engineer/44408/92638132304?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_df4d6de3-e52

## Description

Our team at Synopsys is seeking an IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer to join our team. As a key member of our design implementation team, you will be responsible for designing and implementing high-speed interface IP subsystems for various applications, including AI acceleration, GPGPU, and Big-Data SOC chips.

Key qualifications:

- Minimum 5+ years of experience in IP/ASIC/SOC design implementation

- Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.

- Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR

- Good communication skills while interacting with internal teams and customers

Preferred Experience:

- Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass

- Experience in DesignWare Core IPs or PHYs

- Experience in TCL, Perl, Python, or other shell scripting

As a member of our team, you will have the opportunity to work on cutting-edge projects and collaborate with experienced engineers. You will also have access to state-of-the-art tools and technologies, as well as opportunities for professional growth and development.

Benefits:

- Comprehensive medical and healthcare plans

- Time away programs (ETO and FTO)

- Family support (maternity and paternity leave, parenting resources, adoption and surrogacy assistance)

- ESPP (purchase Synopsys common stock at a 15% discount)

- Retirement plans

- Competitive salaries

If you are a motivated and experienced engineer looking for a new challenge, please submit your application.

## Skills

### Required
- IP/ASIC/SOC design implementation
- synthesis
- timing optimization
- SDC writing
- CDC/RDC checking
- PCIe
- USB
- Display Port
- Ethernet
- DDR

### Nice to have
- Design Compiler
- Fusion Compiler
- PrimeTime
- Spyglass
- VC Spyglass
- DesignWare Core IPs
- PHYs
- TCL
- Perl
- Python
- shell scripting

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/beijing/ip-pcie-cxl-usb-dp-subsystem-design-implementation-engineer/44408/92638132304?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)