# Senior System Integration Engineer, Memory

**Company**: NVIDIA
**Work arrangement**: remote
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-System-Integration-Engineer--Memory_JR2022380?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_dec9d32b-933

## Description

NVIDIA's Silicon Co-Design Group (SCG) leads the full product development lifecycle, from early architecture definition through silicon bringup to product release. The ArchDev team is the hub for silicon and system-level feature development, driving tradeoff analysis, system integration, and POR alignment across the entire organization.

As a Senior Memory Systems Engineer, you will own HBM and LPDDR integration in sophisticated SoCs. This role covers the full stack, including silicon, package, embedded software, testing, and product development. You will resolve the toughest system-level memory challenges throughout the process, building solutions that hold up at scale.

**Responsibilities:**

- HBM & LPDDR System Integration and Bringup: Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs.

- Full-Stack Memory Closure: Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware.

- Post-Silicon Margining, VF Shmoo & Correlation: Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency.

- Memory Debug: Debug and resolve memory training, calibration, SI/PI, and system-level stability issues.

- Validation & Characterization Planning: Define validation, characterization, and issue-tracking plans across chip programs.

**Requirements:**

- BS or MS in EE/CE , or equivalent experience.

- 12+ years in HBM, LPDDR, or high-speed memory systems, with hands-on depth in silicon bringup, characterization, and debug at scale.

- Deep command of SI/PI, timing, margining, and memory training behavior.

**Benefits:**

- Equity

- Benefits

## Skills

### Required
- HBM
- LPDDR
- SI/PI
- memory systems
- silicon bringup
- characterization
- debug

### Nice to have
- HBM3/HBM3E
- JEDEC margins
- thermal-electrical co-sim
- ECC methodology
- power management
- LLM-assisted debug
- root cause analysis

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