# P&R Implementation Senior Staff Engineer

**Company**: Synopsys
**Location**: Seongnam-si, Gyeonggi-do
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/seongnam-si/p-and-r-implementation-senior-staff-engineer/44408/102756615248?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_de0c2fea-7e6

## Description

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.

As a P&R Implementation Senior Staff Engineer at Synopsys, you will play a critical role in driving foundry testchip projects from floorplan through tapeout, working directly with Synopsys advanced node enablement teams to validate new process technologies.

**Responsibilities**

- Drive foundry testchip projects from floorplan through tapeout, working directly with Synopsys advanced node enablement teams to validate new process technologies

- Develop and refine foundry implementation and 3DIC solutions aligned with Synopsys reference methodology, ensuring they work in real customer environments

- Provide hands-on engineering support to foundry partners and end customers on DTCO, PPA optimization, and testchip bringup challenges

- Debug complex P&R, timing, and physical verification issues using Fusion Compiler, PrimeTime, StarRC, IC Validator, and RedHawk across multi-die and advanced packaging contexts

- Coordinate with foundry partners, internal Synopsys product teams, and customer design teams to resolve implementation flow bottlenecks and drive adoption of Synopsys tools

- Collaborate with field account teams and foundry jumpstart teams to support mutual customer engagements and accelerate tool deployment

- Explore and integrate productivity improvements through automation, scripting, and AI-assisted engineering tools like Cursor to enhance design closure efficiency

**The Impact You Will Have**

- Enable successful tapeouts on advanced nodes by delivering high-quality physical design implementation for early testchips that validate new foundry processes

- Accelerate customer adoption of Synopsys Fusion Compiler and 3DIC solutions, directly influencing design wins and long-term tool loyalty

- Push the boundaries of what is achievable in Power, Performance, and Area through hands-on design optimization and methodology refinement

- Resolve critical design and flow issues that would otherwise block customer schedules, protecting revenue and strengthening foundry partnerships

- Shape the next generation of Synopsys reference flows by feeding real-world learnings back into product and methodology teams

- Mentor engineering teams across geographies, raising the technical bar for physical design execution and signoff quality

- Build trust with foundry partners and end customers by consistently delivering solutions that work under pressure and on schedule

**Requirements**

- Bachelor's or Master's in Electrical Engineering with 8+ years of hands-on physical design experience

- Deep expertise in place and route methodology, top-level implementation, and P&R timing signoff using Synopsys Fusion Compiler

- Proven experience in high-performance and low-power physical design, including full-chip PPA optimization and design closure

- Strong hands-on experience with physical design signoff tools such as PrimeTime, StarRC, IC Validator, and RedHawk or equivalent solutions

- Track record of contributing to real SoC, CPU, or GPU tapeouts, ideally on advanced nodes (7nm or below)

- Strong debugging and problem-solving skills, particularly in resolving complex timing, DRC, LVS, and IR drop issues

- Experience working with foundry PDKs and design rule decks is essential

**Benefits**

- Comprehensive medical and healthcare plans that work for you and your family

- Time away programs, including ETO and FTO

- Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance

- ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back

- Retirement plans that vary by region and country

- Competitive salaries

## Skills

### Required
- Electrical Engineering
- Physical Design
- Place and Route Methodology
- Fusion Compiler
- PrimeTime
- StarRC
- IC Validator
- RedHawk

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/seongnam-si/p-and-r-implementation-senior-staff-engineer/44408/102756615248?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)