# Principal Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)

**Company**: Synopsys
**Location**: Hyderabad, Telangana
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/hyderabad/principal-digital-verification-engineer-memory-interface-ip-hbm-ddr-lpddr/44408/100624923952?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_dd5b1af0-ce6

## Description

You will be joining Synopsys, a leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products.

As a Principal Digital Verification Engineer, you will focus on Memory Interface IP, specifically HBM, DDR, and LPDDR protocols.

Your responsibilities will include:

- Designing and building verification environments for Interface IP protocols using SystemVerilog and UVM

- Writing detailed test plans covering functional scenarios, corner cases, and protocol compliance

- Developing reusable verification IP and testbenches adaptable across multiple projects and IP variants

- Collaborating with design and architecture teams to identify bugs and clarify specifications

- Running functional coverage analysis and driving coverage closure

- Mentoring junior verification engineers on UVM best practices and verification strategy

- Using simulation tools like VCS or ModelSim to execute regression suites and debug failures

The impact you will have includes:

- Delivering Interface IP that powers memory subsystems in AI accelerators, mobile SoCs, and high-performance computing platforms

- Reducing post-silicon bugs and customer escalations through rigorous verification

- Shaping verification methodology and standards for next-generation memory IP products

- Accelerating project schedules by building reusable verification components

- Raising the technical bar across the verification team through mentorship

Requirements include:

- Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8 to 10+ years of hands-on ASIC or SoC verification experience

- Proven track record verifying Interface IP protocols such as HBM, DDR, LPDDR, or AMBA

- Strong proficiency in SystemVerilog and UVM

- Deep understanding of digital design concepts, timing, protocol compliance, and memory subsystem architecture

- Experience with simulation tools like VCS, ModelSim, Xcelium, or equivalent

- Demonstrated ability to drive functional coverage closure and deliver fully verified IP on schedule

Benefits include comprehensive health, wellness, and financial packages, with specific offerings varying by region and country.

## Skills

### Required
- SystemVerilog
- UVM
- ASIC verification
- HBM
- DDR
- LPDDR
- AMBA
- VCS
- ModelSim

### Nice to have
- HBM2
- HBM3
- DDR4
- DDR5
- LPDDR4
- LPDDR5

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/hyderabad/principal-digital-verification-engineer-memory-interface-ip-hbm-ddr-lpddr/44408/100624923952?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)