# ASIC Digital Design, Sr Staff Engineer

**Company**: Synopsys
**Location**: Hyderabad, Telangana
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/hyderabad/asic-digital-design-sr-staff-engineer/44408/101997038144?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_dc44c2cc-553

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are a passionate and detail-oriented ASIC Digital Design professional who thrives in high-tech, fast-paced environments. With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results. You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry.

**Responsibilities:**

- Lead and execute scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex ASIC designs.

- Work closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.

- Analyze and resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.

- Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.

- Collaborate with cross-functional teams to define and implement best practices for DFT methodologies and flows.

- Contribute to the continuous improvement of automation scripts and design flows to boost efficiency and reduce turnaround time.

**Requirements:**

- Extensive hands-on experience with 3-10yrs in DFT methodologies, including scan insertion and ATPG for complex ASIC designs.

- Proficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites.

- Strong understanding of digital logic design, RTL coding, and verification principles.

- Demonstrated ability to debug and resolve DFT-related issues across multiple project phases.

- Solid scripting skills (e.g., TCL, Perl, Python) to automate design and test flows.

**Benefits:**

- Comprehensive medical and healthcare plans that work for you and your family.

- In addition to company holidays, we have ETO and FTO Programs.

- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

- Save for your future with our retirement plans that vary by region and country.

- Competitive salaries.

## Skills

### Required
- DFT methodologies
- scan insertion
- ATPG
- Spyglass DFT
- scan STA
- digital logic design
- RTL coding
- verification principles
- scripting skills

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/hyderabad/asic-digital-design-sr-staff-engineer/44408/101997038144?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)