# Senior Logic Design Engineer, Cache Coherent Interconnects

**Company**: NVIDIA
**Location**: Santa Clara
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Logic-Design-Engineer--Cache-Coherent-Interconnects_JR2014881?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_d7bc7708-613

## Description

We are now looking for a Senior Logic Design Engineer!

As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation.

This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence!

**Responsibilities:**

- As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip.

- Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation.

- Collaborate with our verification team to verify the correctness of your unit.

- Work with implementation to achieve your timing, area, performance and power goals.

- Assist with timing closure of super units.

**Requirements:**

- Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.

- 5+ years of experience in processor or other related high performance semiconductor designs.

- Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

- Strong communication and interpersonal skills are required along with the work in a dynamic, global team. Your successful track record of mentoring junior engineers and interns a huge plus.

- A strong background in computer architecture, cache coherency or high speed interconnects is helpful

You will also be eligible for equity and benefits.

## Skills

### Required
- Verilog
- RTL design
- Verification
- Logic synthesis
- Prototyping
- DFT
- Timing analysis
- Floor-planning
- ECO
- Bring-up & lab debug

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Logic-Design-Engineer--Cache-Coherent-Interconnects_JR2014881?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)