# Senior ASIC Floorplan Design Engineer

**Company**: NVIDIA
**Location**: Santa Clara
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Floorplan-Design-Engineer_JR2017652?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_d7aabf90-94d

## Description

We are now looking for a Senior ASIC Floorplan Design Engineer!

NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic company.

**Responsibilities:**

- Work with architects, design leads, physical design leads and package leads to develop and craft and optimize floorplans during early chip development.

- Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.

- Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.

- Build tools and improve existing infrastructure to optimize chip area and speed of execution.

**Requirements:**

- Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.

- 12+ years of relevant work experience.

- A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.

- Experience in Verilog, System Verilog or similar HVL.

- Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.

- Strong communication and interpersonal skills and ability & desire to work as a great teammate.

- Python, Perl and C/C++ programming language experience.

**Benefits:**

- Eligible for equity and benefits.

## Skills

### Required
- Verilog
- System Verilog
- HVL
- CAD
- physical design methodologies
- chip floorplan
- power/clock distribution
- packaging
- P&R
- timing closure
- Python
- Perl
- C/C++

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Floorplan-Design-Engineer_JR2017652?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)