# ASIC Design and Physical Implementation Engineer

**Company**: Cisco
**Location**: Yerevan
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Armenia/ASIC-Physical-Design-Engineer_2025096?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_d4976740-007

## Description

This is a hybrid role with four days per week at Cisco’s Yerevan office.

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development,from design to qualification to production,is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Lead macro-level RTL-to-GDSII physical implementation and signoff. Collaborate with Front-End teams to translate architecture into optimal physical design. Perform synthesis, floorplanning, placement, Clock Tree Synthesis, and routing. Optimize power, performance, and area while maintaining design correctness through formal verification. Execute static timing analysis, physical verification, formal checks, and signoff closure to ensure reliable, high-quality silicon. Analyze and resolve Electromigration and IR-drop issues to meet reliability and performance signoff targets.

**Minimum Qualifications**

- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.

- 5+ years of hands-on experience in ASIC design and physical implementation.

- Proven track record in ASIC physical design and verification preferably in complex SoC or block-level projects.

- Deep knowledge of block-level synthesis, place-and-route (PnR), and timing closure.

- Experience with industry-standard PnR and signoff tools (e.g., Synopsys, Cadence).

**Preferred Qualifications**

- Broad understanding of physical design methodologies, integration, and implementation flows.

- Experience in physical verification (LVS, DRC) and signoff processes.

- Familiarity with physical design EDA toolchains and end-to-end workflows.

- Advanced expertise in STA, timing closure, and constraint management.

- Proficiency in scripting (Tcl, Python, or Perl) for automation and productivity improvements.

## Skills

### Required
- ASIC design
- physical implementation
- RTL-to-GDSII
- synthesis
- floorplanning
- placement
- Clock Tree Synthesis
- routing
- formal verification
- static timing analysis
- physical verification

### Nice to have
- physical design methodologies
- integration
- implementation flows
- signoff processes
- EDA toolchains
- STA
- timing closure
- constraint management
- scripting

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Armenia/ASIC-Physical-Design-Engineer_2025096?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)