# Intern ASIC TOP Floorplan Design Engineer

**Company**: NVIDIA
**Experience**: internship
**Job type**: internship
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/ASIC-TOP-Floorplan-Intern--2027_JR2027469?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_d45da732-b76

## Description

NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's leading SoC's and GPU's. This position offers a unique opportunity to craft and influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

**Responsibilities:**

- Working with architects, design leads, physical design leads and package leads, you will develop and craft and optimize floorplans during early chip development.

- Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.

- Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.

- You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

**Requirements:**

- Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work/learning experience.

- Experience in Verilog, System Verilog or similar HVL.

- Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.

- Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.

- Python, Perl and C/C++ programming language experience.

**Preferred Qualifications:**

- Experience in driving development of large scale ASIC floorplan is a huge plus.

## Skills

### Required
- Verilog
- System Verilog
- CAD
- physical design methodologies
- Python
- Perl
- C/C++

### Nice to have
- large scale ASIC floorplan development

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/ASIC-TOP-Floorplan-Intern--2027_JR2027469?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)